1. Technical Field
The present disclosure relates to a semiconductor device and, more particularly, to a semiconductor device having an output buffer initialization circuit to prevent the loss of data output from a memory device just after another memory device is powered up in a multi-chip package (MCP) having at least two memory devices, and also to an output buffer initialization method.
2. Discussion of Related Art
A multi-chip package (MCP) is a multi-chip device in which various types of memory chips are stacked in a single package. The MCP may combine necessary memories according to applied products, and is a semiconductor device contributing greatly to the efficient use of space in a portable device, such as a mobile phone.
FIG. 1 is a functional block diagram of a general MCP. Referring to FIG. 1, the MCP 10 includes a first, memory 20 and a second memory 30. The first memory 20 and the second memory 30 can be embodied by volatile memory devices such as RAMs or non-volatile memory devices such as ROMs, EEPROMs, or flash memories.
The first memory 20 includes a first memory cell array 22, a first peripheral circuit 24, and a first output buffer 26. The first memory cell array 22 includes a plurality of memory cells arranged in a matrix of rows and columns. The first peripheral circuit 24 writes data to a predetermined cell of the first memory cell array 22 and reads out and amplifies the written data. The first output buffer 26 outputs cell data amplified by the first peripheral circuit 24.
The second memory 30 includes a second memory cell array 32, a second peripheral circuit 34, and a second output buffer 36. The second memory cell array 32 includes a plurality of memory cells arranged in a matrix of rows and columns. The second peripheral circuit 34 writes data to a predetermined cell of the second memory cell array 32 and reads out and amplifies the written data. The second output buffer 36 outputs cell data amplified by the second peripheral circuit 34.
FIG. 2 is a functional block diagram of the output buffer of a conventional semiconductor device. FIG. 3 is a circuit diagram of an output buffer initialization circuit of the conventional semiconductor device shown in FIG. 2. Referring to FIGS. 1 through 3, the output buffer 26 or 36 of the semiconductor device 10 includes an output buffer initialization circuit 50 and an output buffer circuit 60.
The output buffer initialization circuit 50 receives a first set signal EVCCHB generated in response to the power up of a semiconductor memory device, for example, the first memory 20 of FIG. 1, and a second set signal PDPDE enabling the power down of the semiconductor memory device and generates an output buffer reset signal EVCCHB_DQ.
Referring to FIG. 3, the output buffer initialization circuit 50 includes a logic gate block 52 and a level shifter 54. The logic gate block 52 receives the first set signal EVCCHB and the second set signal PDPDE, performs a predetermined logic operation, and outputs a logic operation result C1. The level shifter 54 receives the logic operation result C1, converts the logic operation result C1 to a predetermined level, and outputs the output buffer reset signal EVCCHB_DQ.
The MCP 10 is formed by integrating various types of memory devices 20 and 30 in a single package. The output data of the memory devices 20 and 30 is output from a common output port (not shown). Thus, when any one of the memory devices, for example, the first memory 20, is powered up, the output data of the other memory device, for example, the second memory 30, may be affected. That is, an output end of the first output buffer 26 does not affect the data output from the other memory device (30) when it only maintains a high impedance (Hi-z) state.
When the first memory 20 is powered up and a clock signal CLKDQ input to the output buffer circuit 60 maintains a low level “0”, however, the output buffer, for example, the first output buffer 26, becomes a low impedance state and may affect the data output from the other memory chip, for example, the second memory 30.
For example, when the clock signal CLKDQ maintains the low level “0”, a pull-up transistor (not shown) or a pull-down transistor (not shown) included in the output buffer, for example, the first output buffer 26, may be tamed on by a leakage current flowing in a PMOS transistor or an NMOS transistor (not shown) constituting the output buffer circuit 60. Accordingly, an output node of the output buffer 26 can be in a low impedance state such that it may affect the data output from the other memory chip, for example, the second memory 30.